The course material covers a two and a half week introduction to VERILOG programming. Prior to these exercises, students have been exposed to basic analog and digital circuits, C programming and basic analog to digital and digital to analog converter concepts.
The hardware for the exercises consists of Digilent BASYS boards (with peripheral modules) which utilize a Xilinx Spartan 3-E FPGA. The Verilog programming is done with the (free) Xilix WebPack. The boards are programmed with the (free) Adept Software Suite.
The exercises cover the following topics:
|Basic Verilog Syntax: modules, instantiation of modules, branching statements;|
|Pin assignment for wires and buses;|
|Combinational and Sequential Logic implementation.|
In the exercises, the students implement:
|a simple 4 bit adder with a 7-Segment decimal display;|
|a radiation counter with a 7-Segment decimal display;|
|a simple Pulse Width Modulation (PWM) algorithm to control the brightness of an LED;|
|a Sigma-Delta PWM algorithm to make an Analog to Digital converter to play 8 and 16 bit music stored on flash memory modules.|
The documentation and lab manual can be downloaded here.
The supporting Verilog modules can be found here: (Copy the content to a Verilog file with "v" extension.)
|HexDisplayV1.v: Verilog 7-Segment LED display module with HEX to Decimal conversion;|
|PWM_Modules.v: Verilog Pulse Width Modulation modules: Simple and Sigma Delta alghoritm;|
|FlashMemModules6.v: Verilog modules
to read (and write to) the Digilent 16 Mbit Flash MemoryPeripheral Module
|The schematic for the interface board that connects the Aware Electronics RM60 Geiger Mueller tubes to BASYS board can be found here.|
Note: the Verilog Modules and the Lab Excercises have been developed by Kurt Wick at the University of Minnesota. You may download and use them (at your own risk) for personal or educational use; they may not be used for commercial use.